Digital Signal Processing

P. S. RajaKumar ¹, S. Ravi ², R. M. Suresh ³

Affiliations
1 JNT University, Hyderabad, IN
2 Electronics and Communication Engineering Department at Dr. M.G.R. Educational and Research Institute, Maduravoyal, Chennai – 600 095, IN
3 Department at RMD Engineering College, Kavarapet, Gummudipoondi, IN

Abstract

To compare the performance of two speech coders, it is necessary to have some indicator of the intelligibility and quality of the speech produced by each coder. The term intelligibility usually refers to whether the output speech is easily understandable, while the term quality is an indicator of how natural the speech sounds. It is possible for a coder to produce highly intelligible speech that is low quality in that the speech may sound very machine-like and the speaker is not identifiable. On the other hand, it is unlikely that unintelligible speech would be called high quality, but there are situations in which perceptually pleasing speech does not have high intelligibility. We briefly discuss here the most common measures of intelligibility and quality used in formal tests of speech coders.

Keywords

Speech Coder, Speech Communication, Speech Enhancement, Speech Recognition, Speech Signal.

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N. Vinothkumar ¹, V. Vignesh ¹, S. Ravi ²

Affiliations
1 VIT University, Vellore, Tamilnadu, IN
2 School of Electronics, Vellore Institute of Technology, University Vellore, Tamilnadu, IN

Abstract

This paper presents the design of adders using the ultra low power two phase clocked adiabatic logic. Using this logic the basic NAND, NOR, EXOR is designed for designing the 8bit ripple carry adder and the D-flip-flop is constructed using the adiabatic NAND logic and the shift register is evaluated using the D flip-flop to design the serial adder and the performance parameters such as energy dissipation, frequency of operation, are compared with static CMOS and from the results found that it saves up to 70% of power.

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